GC

Embedded Memory Push

by Kosta Andreadis - October 25, 1999, 7:47 am PDT
Source: EETimes

Some details on the hardware being developed for Dolphin.

EETimes reports Toshiba has followed suit and are planning to transfer embedded-DRAM process to Taiwan's Winbond Electronics Corp. and World Semiconductor Manufacturing Corp., and NEC will invest about $755 million on a fab to make Nintendo's graphics chip, which uses a one-transistor SRAM cell from MoSys Inc. (Sunnyvale, Calif.). The fab will also build a discrete high-speed DRAM for Dolphin. Though the fab's first target is Dolphin, the line could be used for other chips based on NEC's UX4 process in the future.

Toshiba Corp. is quietly making plans to transfer its embedded-DRAM process to a pair of Taiwanese wafer foundries following the collapse of its agreement with Singapore-based Chartered Semiconductor Manufacturing Ltd., EE Times has learned. The news comes on the heels of an announcement that NEC Corp. will build a wafer fab for graphics chips using an alternative embedded memory for Nintendo Co.'s next-generation game console, code-named Dolphin.

Taken together, the two moves suggest that conventional embedded DRAM is still slogging ahead while alternative approaches are picking up the pace. "Memory vendors all hoped embedded DRAM would be a way out of a horrible market situation, but it hasn't materialized that way," said Jim Handy, memory analyst for Dataquest Inc. (San Jose, Calif.).

NEC will invest about $755 million on a fab to make Nintendo's graphics chip, which uses a one-transistor SRAM cell from MoSys Inc. (Sunnyvale, Calif.). The fab will also build a discrete high-speed DRAM for Dolphin.

"The load of [embedded-memory] chips on a line is heavy," said Keiichi Shimakura, associate senior vice president of NEC. "It is impossible to make such chips on our existing lines. We need a new line."

Though the fab's first target is Dolphin, the line could be used for other chips based on NEC's UX4 process in the future.

However, Pixelworks became the latest MoSys licensee this past week, when it chose the company's one-transistor, or 1T, technology for use in a future display controller. Since it decided to offer its proprietary technology to outside vendors in August 1998, MoSys has announced licensing deals with NEC, Analog Devices Inc. and Taiwan Semiconductor Manufacturing Co. It has also signed nondisclosure agreements with more than 30 companies, including Chartered, said Mark-Eric Jones, vice president and general manager of intellectual property for MoSys.

"We do have some customers that are interested in [MoSys]," said Ana Hunter, vice president of worldwide electronic design for Chartered. "We've had discussions with [MoSys] to prove out the technology. If our customers are interested in that IP [intellectual property], then we will evaluate it."

Although MoSys calls its technology an embedded SRAM for marketing reasons, it is actually an embedded DRAM: DRAMs have one transistor and one capacitor in each storage location, while SRAMs have four- or six-transistor cells, said Steve Przybylski, principal consultant with Verdande Group.

"The primary characteristics of DRAM are relatively long access times and complexity associated with row- and-column accesses and refresh," he said. "MoSys has hidden all of that complexity and dramatically decreased the access time, to make the memory array behave like SRAM, but with most of the density advantage of DRAM. They're trying to deliver the best of both worlds, and coming close."

Knowing the trade-offs

The MoSys approach has a clear advantage when there is a requirement for intermediate density plus high speed and bandwidth, Przybylski said. Traditional embedded DRAM is better-suited for applications requiring large densities, but where access time poses less of a problem for the designer.

One reason MoSys' 1T cell is an attractive alternative to embedded DRAM or SRAM is that it is process-technology neutral, so it can be used either in a pure logic process or a merged DRAM process, said MoSys' Jones.

"We're not talking about breaking any design rules. If we use a pure logic process, the overall die area is three times better than SRAM. But in the same geometry using embedded DRAM we can also implement a 1T SRAM on that process. If embedded DRAM is an option, we can give you SRAM speed out of that DRAM process. You then end up with a density that is pretty close to embedded DRAM — within 10 to 20 percent. You can get halfway to DRAM density without changing the process at all."

Toshiba's Richmond acknowledged that while strong in graphics chips, embedded DRAM hasn't found a niche everywhere. "We never anticipated it being a high-volume commodity, where you merge a discrete DRAM and a discrete ASIC and see a price reduction," he said. "The technology is for increasing the performance of a memory and lowering cost." For products like disk drives, which "don't typically need that increased performance . . . the cost structures don't match."

Earlier this year, some chip vendors modified their eDRAM process technologies to squeeze out costs while exploring unorthodox variations. The hope was that at the 0.18-micron generation, more designers would look toward embedded DRAM to boost performance and possibly find an answer to the design-reuse quandary.

Samsung, for example, which has staked its burgeoning ASIC business on the wide use of embedded DRAM, began putting its money into the development of both a DRAM-centric process and a premium DRAM-cum-logic process technology.

The strategy was two-pronged: to deploy a DRAM-based technology for cost-sensitive PC peripheral applications such as hard-disk drives that can sacrifice logic speed; and to create a premium, unified process technology that aims for high-density memory and fast logic for graphics chips, game machines and network applications that need speedy logic performance.

For other applications, such as networking, Toshiba this year has worked with design house Mosaid Technologies Inc. (Ottawa) on a handcrafted networking chip containing multiple forms of memory, including DRAM, SRAM, FIFOs, flash and content-addressable memory (CAM).

EETimes reports Toshiba has followed suit and are planning to transfer embedded-DRAM process to Taiwan's Winbond Electronics Corp. and World Semiconductor Manufacturing Corp., and NEC will invest about $755 million on a fab to make Nintendo's graphics chip, which uses a one-transistor SRAM cell from MoSys Inc. (Sunnyvale, Calif.). The fab will also build a discrete high-speed DRAM for Dolphin. Though the fab's first target is Dolphin, the line could be used for other chips based on NEC's UX4 process in the future.

Toshiba Corp. is quietly making plans to transfer its embedded-DRAM process to a pair of Taiwanese wafer foundries following the collapse of its agreement with Singapore-based Chartered Semiconductor Manufacturing Ltd., EE Times has learned. The news comes on the heels of an announcement that NEC Corp. will build a wafer fab for graphics chips using an alternative embedded memory for Nintendo Co.'s next-generation game console, code-named Dolphin.

Taken together, the two moves suggest that conventional embedded DRAM is still slogging ahead while alternative approaches are picking up the pace. "Memory vendors all hoped embedded DRAM would be a way out of a horrible market situation, but it hasn't materialized that way," said Jim Handy, memory analyst for Dataquest Inc. (San Jose, Calif.).

NEC will invest about $755 million on a fab to make Nintendo's graphics chip, which uses a one-transistor SRAM cell from MoSys Inc. (Sunnyvale, Calif.). The fab will also build a discrete high-speed DRAM for Dolphin.

"The load of [embedded-memory] chips on a line is heavy," said Keiichi Shimakura, associate senior vice president of NEC. "It is impossible to make such chips on our existing lines. We need a new line."

Though the fab's first target is Dolphin, the line could be used for other chips based on NEC's UX4 process in the future.

However, Pixelworks became the latest MoSys licensee this past week, when it chose the company's one-transistor, or 1T, technology for use in a future display controller. Since it decided to offer its proprietary technology to outside vendors in August 1998, MoSys has announced licensing deals with NEC, Analog Devices Inc. and Taiwan Semiconductor Manufacturing Co. It has also signed nondisclosure agreements with more than 30 companies, including Chartered, said Mark-Eric Jones, vice president and general manager of intellectual property for MoSys.

"We do have some customers that are interested in [MoSys]," said Ana Hunter, vice president of worldwide electronic design for Chartered. "We've had discussions with [MoSys] to prove out the technology. If our customers are interested in that IP [intellectual property], then we will evaluate it."

Although MoSys calls its technology an embedded SRAM for marketing reasons, it is actually an embedded DRAM: DRAMs have one transistor and one capacitor in each storage location, while SRAMs have four- or six-transistor cells, said Steve Przybylski, principal consultant with Verdande Group.

"The primary characteristics of DRAM are relatively long access times and complexity associated with row- and-column accesses and refresh," he said. "MoSys has hidden all of that complexity and dramatically decreased the access time, to make the memory array behave like SRAM, but with most of the density advantage of DRAM. They're trying to deliver the best of both worlds, and coming close."

Knowing the trade-offs

The MoSys approach has a clear advantage when there is a requirement for intermediate density plus high speed and bandwidth, Przybylski said. Traditional embedded DRAM is better-suited for applications requiring large densities, but where access time poses less of a problem for the designer.

One reason MoSys' 1T cell is an attractive alternative to embedded DRAM or SRAM is that it is process-technology neutral, so it can be used either in a pure logic process or a merged DRAM process, said MoSys' Jones.

"We're not talking about breaking any design rules. If we use a pure logic process, the overall die area is three times better than SRAM. But in the same geometry using embedded DRAM we can also implement a 1T SRAM on that process. If embedded DRAM is an option, we can give you SRAM speed out of that DRAM process. You then end up with a density that is pretty close to embedded DRAM — within 10 to 20 percent. You can get halfway to DRAM density without changing the process at all."

Toshiba's Richmond acknowledged that while strong in graphics chips, embedded DRAM hasn't found a niche everywhere. "We never anticipated it being a high-volume commodity, where you merge a discrete DRAM and a discrete ASIC and see a price reduction," he said. "The technology is for increasing the performance of a memory and lowering cost." For products like disk drives, which "don't typically need that increased performance . . . the cost structures don't match."

Earlier this year, some chip vendors modified their eDRAM process technologies to squeeze out costs while exploring unorthodox variations. The hope was that at the 0.18-micron generation, more designers would look toward embedded DRAM to boost performance and possibly find an answer to the design-reuse quandary.

Samsung, for example, which has staked its burgeoning ASIC business on the wide use of embedded DRAM, began putting its money into the development of both a DRAM-centric process and a premium DRAM-cum-logic process technology.

The strategy was two-pronged: to deploy a DRAM-based technology for cost-sensitive PC peripheral applications such as hard-disk drives that can sacrifice logic speed; and to create a premium, unified process technology that aims for high-density memory and fast logic for graphics chips, game machines and network applications that need speedy logic performance.

For other applications, such as networking, Toshiba this year has worked with design house Mosaid Technologies Inc. (Ottawa) on a handcrafted networking chip containing multiple forms of memory, including DRAM, SRAM, FIFOs, flash and content-addressable memory (CAM).

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